Hiroshi Ishizuka1, Sung James C.2,3,4, Marehito Aoki5,Haedo Jeong6 and Sung Michael7
(1.Tomei Die International Co., Ltd., Akasaka Tokyu Bldg. 11F, 14-3 Nagatacho 2-Chome,
Chiyoda-ku, Tokyo 100-0014, Japan.)
(2.KINIK Company, 64, Chung-San Rd., Ying-Kuo, Taipei Hsien 239, Taiwan)
(3.National Taiwan University, Taipei 106, Taiwan)
(4.National Taipei University of Technology, Taipei 106, Taiwan)
(5.Tomei Diamond Co., Ltd., Oyama Plant, 4-5-1 Jyoto, Oyama, Tochigi 323-0807, Japan.)
(6.G&P Technology, Inc., South Korea.)
(7.Advanced Diamond Solutions, Inc., 351 King Street Suite 813, San Francisco, CA 94158, U.S.A.)
Abstract Low stress polishing is required for the manufacture of advanced integrated circuits (IC) with node sizes of 45 nm and smaller. However, the CMP community achieved the low stress by reducing the down force that press the wafer against a rotating pad. The reduced down force also decrease the removal rate of the wafer. As a result, the productivity suffers. In order to cope with this problem, an electrical potential is applied to the copper layer during polishing, in this case, the chemical oxidation is accelearated and hence the romoval rate. Alternatively, the rotating pad must be softened to minimize the defects of wafers caused by CMP.
In this research, we report a simpler solution to achieve low stress polishing without investing in new equipment and in developing new pad materials. The conventional CMP is proceeded by dressing the pad with a PCD dresser that can form 10*more asperities on the pad surface. The fluffy surface can then polish delicate IC without using the brutal force. As a result, the removal rate of wafers can be maintained without causing defectivity on the IC layer.